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I doubt you will need to recompile, although doing so is often a good idea as new compilers can use new instructions/optimizations.

I’d bet money that the different ISAs are full x86 and a subset of x86 which is a great idea. X86 has a lot of old instructions that almost No one uses. Perhaps the small cores will trap and move to process to the big core if it uses an old instruction.



> I’d bet money that the different ISAs are full x86 and a subset of x86

You don't even need to bet, it's in the article:

"Both SKUs will feature one big ‘Sunny Cove’ CPU core, along with four little ‘Tremont’ Atom CPU cores"

It's a different uArch, but the same ISA. The extension support would be the only concern here, which is super minor.


Guess that makes it very good bet ;)


I don't see how the cost of supporting outmoded instructions would be significant. The decoder is a tiny proportion of the die, and not a bottleneck at all. Obsolete instructions that can't be translated to the same uops everything else uses are already microcoded anyway.

I'd bet the instruction set difference is mainly level of SIMD support. Sunny Cove will have AVX2, Tremont won't have enough execution units to go wider than SSE2.




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